Wednesday, August 16, 2017

An FPGA SDR HF Transceiver, Part 8 -- Front Panel, Rear Panel, and Other Schematics

In this eighth blog post in my FPGA SDR Transceiver series, I will describe the Front Panel and its Arduino processor (and associated circuitry), the Rear Panel, and other circuitry within the radio that interconnects front panel with rear panel.

(Part 7 of this series is here: Part 7)



Before I begin, let me again acknowledge Dick Benson, W1QG.  Dick is the father of this design, and although I've made some modifications to the FPGA logic, the underlying architecture and the vast majority of the Simulink implementation is Dick's.


A note regarding the schematics...

These schematics were drawn using the Lite version of Cadence's Orcad Capture.  This is the free version of the program, and it limits a schematic's number of nets to 75 and the number of parts to 60 (limitations which apply if you want to save the design, which I always do).

Because this radio design has many more nets and parts than the 75/60 limit specified by Cadence, I have broken the overall design into smaller "bite size" schematics, each  independent of the others and each drawn on a single A-size sheet.

But because I've broken up the design into smaller independent pieces, I can not use Capture's Design Rule Checker to check the overall design for design flaws.  Therefore, there is the possibility that errors have crept into the schematics.  So be aware!



This Blog Post is a Work In Progress
and thus
Not Yet Finished!


Summary:

The Front Panel provides the User Interface for the radio, and it is designed to be a separate sub-assembly that can easily be removed from the chassis.

An Arduino Nano processor provides the user-interface processing, and it is tasked with reading the front and rear panel controls, displaying information on the LCD, and communicating with the FPGA.

Let's take a look at the schematics...


Front Panel Main (Nano) Board Schematics:

(Click on image to enlarge)

Notes on the "Main" board schematic:
  1. +12V is supplied to the board via J11 in the lower right-hand corner.  This +12V will also power the FPGA board (via header J1).
  2. +5V is also supplied to the board from a separate source (via J12) -- the Arduino Nano's on-board 5V regulator cannot supply the current required at 5V for the front panel, and so a separate switching power supply provides this assembly's 5V power.
  3. J1 is the primary interface to the FPGA board, and it supports the 4-wire Control Interface, provides +12V to the FPGA board, and carries other miscellaneous IO signals (such as mic audio) between the FPGA board and the Front Panel.
  4. Note that the FPGA Control Interface is a 3.3V interface, whereas the Arduino's IOs are 5V.  R9 and R10 (in conjunction with terminating resistors on the FPGA board) divide down the 5V control signals sent from the Arduino to be 3.3V compliant for the FPGA, and U2 and U3 provide a level translation of FPGA 3.3V output signals to input levels compatible with the Arduino's 5V IO. (Note that the Arduino's ViH spec is 3.0V, minimum, which is slightly higher than the Xilinx FPGA minimum VoH spec of 2.9V.  Thus the level translators to ensure that the Xilinx outputs meet the Arduino's ViH spec.) 
  5. U4 provides 3.3 volts for the Main board.
  6. The front panel's Volume control provides a voltage that is converted to digital by the Arduino (and then sent to the FPGA via the 4-wire Command Interface).
  7. Transmit SWR and Forward Power can also be sampled by the Arduino's ADC via connector J6.  (At this time this feature is not used).
  8. The board also has a buzzer, LS1, to provide various beeps when I press buttons or when error conditions occur.  The Arduino pin driving this beeper can also be used to "calibrate" the Arduino's ADC readings  (to compensate for the actual ADC reference voltage -- necessary if trying to use VRL and VF to calculate SWR and Forward Power).  Its function is selected via header J10.
  9. There are simple one-pole RC filters on many of the IO signals to mitigate susceptibility to RF fields that might be coupled onto external cabling and leads.
  10. LED D2 is an on-board LED used only for debugging and is not visible during normal radio operation (its function is duplicated by a second LED, to be described later, below).

(Click on image to enlarge)

Notes on the "IO1" Schematic:
  1. This schematic shows two headers that provide IO signals to the Arduino.
  2. The upper header, J21, connects to the rotary encoder used for frequency tuning (this is an Oak/Grigby Rotary Optical Encoder, Model 91Q128-43-00110, that provides 128 pulses per revolution).
  3. The lower header, J22, connects to the two front-panel mechanical rotary encoders and the analog meter.  These rotary encoders include push-button switches and are used to select menu items via the LCD.  (They are similar to those used in the Keyes KY-040 rotary encoder module).
  4. Again, simple one-pole RC filters attenuate any RF that might be coupled into the circuitry via external wiring.

(Click on image to enlarge)

Notes on the "IO2" Schematic:
  1. There are more IO signals than there are Arduino IO pins: U1 is an IO expander (PCF8575) that allows the Nano access to the additional IO signals.  It communicates with the Arduino Nano via the Nano's I2C interface.
  2. The RST signal from U1 is a high-true Reset signal, sent to the FPGA board, used for resetting the FPGA's Communications Interface.  Note that the PCF8575 cannot drive its output pins high, so a pullup is needed (R23).
  3. The Arduino also communicates with the LCD via I2C (using an external I2C to parallel converter mounted at the LCD).  Header J2 provides this interface.
  4. Header J16 provides an extra I2C connector.  It is not used at this time.
  5. The microphone audio attaches to the Arduino board via header J13.  Note that the microphone audio is not used by the Arduino -- instead, this signal is simply routed to the 26-pin FPGA interface connector, where it is sent to the FPGA board (and converted into a digital signal).  By the way, this MIC_AUD signal is not from the mic connector itself, but from a separate mic preamp board that will be described later, below).
  6. U4 provides "clean" 5V that can be used to power an active (FET) mic element.  This feature is not used at this time.
  7. Transmitter keying is controlled via the Arduino, and the signal nPTT (low true) is used both in CW and Voice modes to signal the FPGA (via the Arduino) to Transmit.  Because this signal can come from the outside world, I've added ESD protection with TVS1.  (R8 provides both RF filtering and current-limiting if TVS1 were to clamp).
  8. And again, numerous simple RC filters on control lines to filter out RF that might be coupled onto cabling.
  9. The LED is only used for debugging and is not visible during normal operation of the radio.

Connector Locations:

For my own records, below are the location of the Main Board's connectors (shown in the three schematics, above):



Front Panel 5V Switcher:

The Front Panel's 5V requirements are supplied by a 5V switcher that converts 12V to 5 VDC.  (I had originally used an LM7805 linear regulator, but, given the 5V rail's load current, the 7805 was getting too hot for comfort even with a large heat-sink, and so I went the switcher route.

This circuit is mounted on a separate board within the Front Panel assembly (it is not on the Arduino "Main" board).

(Click on image to enlarge)

The circuit should be self explanatory.  For additional information refer to the LM2576 datasheet.


Front Panel Controls:

Now let's look at the wiring of most of the front panel's controls.  (The remaining controls will be described in the next section, below).

This circuitry should be self-explanatory...

(Click on image to enlarge)

(Click on image to enlarge) 


Front Panel Controls, Rear Panel, and Interconnects:

Below are the remaining front panel controls and connectors, as well as rear panel connectors and how they all interconnect.

(Click on image to enlarge)

Notes on the "Interconnections 1" schematic:
  1. On the rear panel, diode D1 provides protection against accidental reversing of the power supply voltage.
  2. J15, the "EXT. ON" connector, provides a signal for external devices that is low-true when the FPGA SDR radio is ON. 
  3. J3 provides a PTT port parallel with the front-panel's "Key" and "MIC" (PTT pin) ports.  Note that this signal, nPTT, is low true (low = xmit).

This next schematic, "Interconnects 2", details the audio output interconnections:

(Click on image to enlarge)

Notes on the "Interconnects 2" schematic:
  1. Speaker Audio from the FPGA board comes into this schematic via connector J12 (at bottom of schematic).
  2. LS1 is the radio's internal speaker (mounted on the top cover).
  3. An external speaker can be connected to the radio via J1 on the back panel.  Plugging in an external speaker will turn OFF the radio's internal speaker.  (Important note: the external speaker should be connected only to Tip and Ring of the stereo plug, NOT to ground).
  4. Although a stereo connector (J2) is used for the headphones, they are connected in MONO mode (left and right in parallel).
  5. And because the speaker audio from the FPGA board is differential with DC bias, this differential signal is converted to single-ended for the headphones by using just one side of the differential signal (against ground).  The DC bias is removed by C1 (i.e. the audio is AC-coupled to the headphone jack).
  6. R3 keeps the negative side of C1 at ground potential so that there isn't a loud "pop" in the headphones when they are plugged into J2.
  7. The SPKR ON switch turns ON or OFF any speaker (internal or extenal), but not headphone audio.  One side of this switch is read by the Arduino, and the switch status is sent to the FPGA where it is used to change the audio level when headphones are used.

*** Schematics of additional rear-panel connectors will go here.

Below is an image showing the interconnects in the two schematics above.

(Click on image to enlarge)

(Note some singeing on the wires going to J12.  Oops!)


LCD Adapter:

To minimize Arduino IO pin usage, the Arduino communicates with the Front Panel LCD via its 2-wire I2C interface.

But because the LCD itself does not support I2C, I use an I2C Interface LCD Adapter similar to the one shown below and available via eBay:


This adapter is designed for use with LCD modules having a 16-pin SIP interface connector.  Unfortunately, the LCD module I chose has a 16-pin DIP interface connector.  So I wired an adapter board (that sits on the back of the LCD module) to convert the I2C Adapter's 16-pin SIP wiring to 16-pin DIP wiring:

(Click on image to enlarge)

Microphone Preamp:

Microphones typically generate low-level audio.  Although the FPGA could internally amplify a low level signal coming into it via the 16-bit audio ADC (the AK4554 Codec), this amplification (following the ADC) also increases the noise-floor underlying the microphone audio.

So I've added an external Mic Preamp (prior to the audio codec) with three levels of gain:  20 dB, 10 dB, and 0 dB.  Its circuit is below:

(Click on image to enlarge)

Notes on the Microphone Preamp:
  1. An on-board 5V regulator (U2) provides "clean" power for the preamp circuitry. 
  2. The op-amp (U1) has rail-to-rail outputs.
  3. One half of the op-amp (U1A) is not used.  I prefer not to have floating inputs on ICs, so I've connected it in a non-inverting configuration with its output set to 2.5V.
  4. The MIC IN connector (J2) connect to the front panel microphone jack.
  5. The MIC OUT connector (J1) connects to the Arduino board, which passes the amplified microphone audio to the FPGA board and the audio codec there.
  6. TVS1 provides ESD protection against an ESD event occurring on the external MIC signal.

Assembly:

The HP case I'm using for the radio is not large, and so to install the Front Panel and its circuitry some creative assembly was required.  The photos below show what is involved...

First, here is the Front Panel with controls, LCD, encoders, and LCD Adapter and 5V switcher mounted (the 5V switcher is mounted (on standoffs) above the Frequency rotary encoder and the LCD Adapter is mounted (on standoffs) above the LCD module):


Next, mounting (on more standoffs) the Main (Arduino) board and the Mic Preamp board above the LCD Module Adapter and 5V switcher boards:


And finally, connecting all of the cables!

(Oh what a tangled web we weave!)


OK.  That's it for this blog post!


Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion


Posts in this Series:

Part 1: Overview
Part 2: FPGA Modulation and Demodulation
Part 3: Interpolation and Decimation Filters
Part 5: Control Interface, Etc.


Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Thursday, July 13, 2017

An FPGA SDR HF Transceiver, Part 7 -- Schematics, RX Signal Chain

In this seventh blog post in my FPGA SDR Transceiver series, I will describe the Receiver input circuitry -- the Receiver's Signal Chain, prior to the ADC:
  • RX Attenuator
  • Broadcast-Band Filter.
  • Anti-Aliasing Filter
  • Preamp and ADC Driver
(Part 6 of this series is here: Part 6)

But first, a teaser photo...


...which shows the radio as it is slowly being assembled into an old HP chassis I've scavenged for this purpose.

And before I begin, let me again acknowledge Dick Benson, W1QG.  Dick is the father of this design, and although I've made some modifications to the FPGA logic, the underlying architecture and the vast majority of the Simulink implementation is Dick's.


A note regarding the schematics...

These schematics were drawn using the Lite version of Cadence's Orcad Capture.  This is the free version of the program, and it limits a schematic's number of nets to 75 and the number of parts to 60 (limitations which apply if you want to save the design, which I always do).

Because this radio design has many more nets and parts than the 75/60 limit specified by Cadence, I have broken the overall design into smaller "bite size" schematics, each  independent of the others and each drawn on a single A-size sheet.

But because I've broken up the design into smaller independent pieces, I can not use Capture's Design Rule Checker to check the overall design for design flaws.  Therefore, there is the possibility that errors have crept into the schematics.  So be aware!


Block Diagram:

(Click on image to enlarge)

Notes on the block diagram:
  • The Receive Signal Chain begins at the T/R relay, shown above in Receive mode.
  • The first block is a variable attenuator, which can select 4 values of attenuation in 6 dB increments.
  • Next is filtering.  Broadcast-band stations in my area can be quite loud, so there is a high-pass filter to attenuate the broadcast band.  
  • And to prevent frequencies greater than half the ADC's sampling rate (that is, 80 MHz / 2, or 40 MHz) from being aliased down to the 0 - 40 MHz range, there is a low-pass anti-aliasing filter.
  • And finally, there are two stages of pre-amplification, which provide a total of 32 dB of gain prior to the ADC.

Note that there is no band-pass filtering prior to the ADC.  That is, as shown above, the receiver's front-end is wide open between 3 and 30 MHz.  So it is very important that the active preamplification stages be low-distortion.

Will additional front-end band-pass filtering be required?  So far the receiver seems to perform well running with its "wide open" front end (and broadcast-band filter).  But I'll give it some time to see how well it performs, and will update this blog if I discover that some sort of front-end band-pass filtering is needed.

RX Attenuator and T/R Switch:

(Click on image to enlarge)

Notes on the RX Attenuator and T/R Switch.
  • The first relay (LS3, in the upper left corner) is simply a "receiver protection relay" that shorts the antenna input (and disconnects the radio circuitry from the antenna) when power is OFF.  (In the summer there are often thunderstorms in the Sierra Nevadas, and I'd like to protect the circuitry when I am not using the radio.
  • Relay LS4 is the T/R relay.  Note that the receiver input is grounded when in TX mode, and the transmitter output is connected to a 50 ohm load when in RX mode.  The relay contacts are connected in parallel, to reduce the possibility of flakey contacts causing problems.
  • The attenuators are nothing special -- standard PI configurations that can be switched in or out.  But note that relay LS2 is a 5V relay (all the others are 12V).  I ran out of 12V relays while building this circuit and so I instead used a 5V relay from my junkbox.  R15 limits its current to about 20 mA (when the DC input voltage is 12V).
  • After the attenuators there is a bit more receiver circuit protection consisting of a fuse and a TVS surge-protection device.  The TVS device should shunt to ground large voltages that exceed its threshold.  In doing so, if the current it is sinking is large (i.e. this is a serious over-voltage event!), the series fuse (63 mA PicoFuse) should blow.  Hopefully both of these devices will protect the receiver front-end circuitry.  (I haven't tested them to verify).
  • The fuse is paralleled with a header to allow me to easily check with an ohmmeter if the fuse has been blown (or short it out, if it has).
  • Diodes are placed across relay coils as standard practice to clamp voltage spikes on a collector of a relay drive transistor (e.g. Q1, Q2, or Q3) when a relay is turned off.  Caps were added across the diodes to shunt any RF (e.g. from nearby transmitters) that might get on the relay control lines.  Probably not needed, but there is no harm in having them.  By the way, the rule of thumb regarding diodes-across-relays is that their forward-current rating should be greater than the relay's "ON" current.  In the case of the relays I am using, their ON current is about 10 mA (at 12 V -- it will be a bit higher if DC power were, say, 13.5V).  (Note, I have not verified if the "rule of thumb" I just mentioned is indeed valid!).
  • Control signals from the FPGA board are filtered with simple one-pole low-pass R-C filters at point-of-entry to this circuit in an attempt to minimize (hopefully) any noise on these lines from being coupled to the sensitive RF front-end circuitry. 

By the way, there are any number of ways to implement an attenuator.  I had originally planned to use a Mini-Circuits DAT-31A-SP Digital Step Attenuator, and had thus planned that the Control I/F for the attenuator, from the FPGA, to consist of 3 bits (Serial Data, Serial Clock, and Latch Enable), in addition to +12V power and the T/R relay control line.  (I changed my mind before implementing this and went the relay route, simply because I did not want to solder the QFN-style package).

Dick (W1QG), on the other hand, rolled his own pin-diode attenuator design, using a UM4000 high-power PIN diode and with the amount of attenuation controlled via a front-panel control (potentiometer).  Regarding his design, here are Dick's words...

The IMD introduced by the PIN diode gain control was quantified.    

The experiment was as follows ....

1) Two  HP 3335A generators were summed.   F1=3.5 MHz  F2=4.0MHz.
2) Summed outputs fed to a variable attenuator which attenuates the summed signal so that the resulting signal, at the ADC, is 1 dB below where the ADC Overload led comes on.
3) Radio tuned to 3.5 and 4 MHz shows 36dB over S9 (that is FS for my rig), full gain (no PIN attenuation)
4) Radio then tuned to 4.5 MHz and signal is S2.  (S2 to S9 is 7*6=42 dB and then add 36 to get 78 dB which would be 84dB  below PEP.)
5) Add in PIN attenuation and the IMD3 term goes no where but DOWN, and quickly disappears. 
6) Radio was then tuned to 7.5 MHz to pick up the IMD2 product which was also S2.
7) The PIN attenuation was then increased as before.
This time the IMD2 did increase to just a bit over S3, but then quickly went down with further PIN attenuation. 
Perfect? No. But more than good enough for me especially since my RF gain control is parked at full tilt 99% of the time. 
Frankly, in retrospect, I probably should not have wasted the panel space for that control J

(Dick added a later note, below).

I had an idea at 0400 this AM regarding the small increase in IMD2 with the onset of the PIN attenuator. 

It precipitated a change (adding a second PIN diode) and this worked as I had hoped:  there is now ZERO increase in IMD2. 

At this point I would call the PIN attenuator PERFECT.  

Broadcast-Band and Anti-Aliasing Filters:

(Click on image to enlarge)

Notes on the Broadcast-Band (BCB) and Anti-Aliasing (AA) Filters:
  • The BCB Filter is a W1QG design.  160 meters is sacrificed to keep the filter simple, otherwise it would need to be more complex if we needed a good 1.8 MHz response while rejecting frequencies of 1.7 MHz and below.
  • Note that if some BCB feedthrough is desired (if you like listening to AM), Dick mentions that replacing the trace to ground (labeled 'A' in the schematic, above) with 16.6 nF of capacitance provides a good compromise between rejecting and passing AM stations.
  • The anti-aliasing filter is a Mini-Circuits RLP-30" surface-mount Low Pass Filter.  I chose it (rather than rolling my own) because of the ease of using it -- I found a seller on eBay who sells PCB boards for mounting them (search eBay for "mini-circuits GP1212 board".  By the way, it isn't that hard to cut your own pattern in copper-clad PCB stock if you'd rather make your own board).
Regarding the Anti-Aliasing Filter specifically:
The goal of the Anti-Aliasing Filter is to reject frequencies above 40 MHz (i.e. above the Nyquist frequency).  The RLP30+ specified -3dB point is actually at 37 MHz, so there will not be too much attenuation of frequencies at 40 MHz or close to 40 MHz (e.g. 45 MHz).

Will this be a problem for me?  I only plan to use this radio to 30 MHz.  For a higher frequency to be "aliased" down to 30 MHz, that frequency would need to be 50 MHz (given the 80 MHz ADC sample rate).  And at 50 MHz, the RLP30+ provides at least 40 dB of attenuation (per my measurements, shown later in this post).

So far this amount of attenuation (and the slope of attenation between 40 and 50 MHz) has proven adequate.  If, with more usage, I find there to be a problem (for example, if there is a nearby high-power 6-meter or FM broadcast station), I can either add some additional filtering to the RLP-30+, or I can replace it with a more complex L-C filter.


Preamp and ADC Driver:

The receiver's front-end gain-stage consists of a Preamp and ADC driver providing roughly 34 dB of gain to the ADC input (max ADC input is +7 dBm for ADC full-scale).

The Preamp consists of two Mini-Circuit's GALI-74 preamps connected in a push-pull configuration (to minimize second-order distortion, compared to a single-ended preamp).  Its gain is about +24 dB:

(Click on image to enlarge)

This stage was actually scavenged from a scrapped TCI board.  Using tin-snips, I cut out the push-pull GALI-74 section of the board from the TCI PCB, removed unnecessary parts, and added SMA connectors and a two-pin header for power:


Notes on the GALI-74 Preamplifier:
  • The preamplifier is push-pull to minimize even-order distortion.
  • Each GALI-74 is biased at 80 mA (for 160 mA, total).
Dick's second gain stage, the ADC Driver, is shown below.  It provides an additional 10 dB of gain:

(Click on image to enlarge)

Notes on the ADC Driver.
  • Again, this stage is push-pull to minimize even-order distortion.
  • Each transistor is biased at about 50 mA of collector current (100 mA, total).
Here's my implementation of this circuit:


To keep the radio's design simple, there is minimal front-end filtering (just an anti-aliasing filter and a broadcast-band reject filter).  So it is very important that the receiver's front end have good IM2 and IM3 performance (the reason why is explained in a bit more detail later in this post, when Dick describes his LTC6433 testing).

Here are my measurements (using my 8568B) of IM3 and IM2 performance of the GALI-74 preamp cascaded with the push-pull ADC driver.  Note that the levels are set so that the PEP output of the cascaded stages is about +7 dBm, which is the level required to drive the ADC input to full-scale:

IM3:


IM2:


For comparison, here are Dick's measurements (measured with his own 8568B) of the IM3 and IM2 performance3 of his GALI-74 preamp cascaded with the push-pull ADC Driver:



Per Dick:  IMD2 is now about 84dB down from PEP and I am pleased with that result.    

For completeness, Dick also ran a Noise Figure measurement on his GALI-74 preamp cascaded with the push-pull ADC Driver:



One more note:  the GALI-74 Preamplifier and the ADC Driver are both powered at +9VDC, which I create with an LM7809 voltage regulator.  I haven't included this regulator in my schematics.    For more information on this design, please refer to the LM78xx series of regulators datasheet for their recommended circuit.


Rx-Chain, Overall Gain and Bandwidth:

Below are my measurements of the Rx-Chain's overall Gain and Bandwidth between the radio's Antenna Port and the Output Port of the Push-Pull ADC Driver stage.

In other words, the overall gain and bandwidth of the circuit blocks circled in orange, below.

(Click on image to enlarge)

To make this measurement, after S21 (i.e. "Response") calibration I added an additional 30 dB of attenuation between my Network Analyzer's output port and the FPGA SDR's antenna port.  Therefore, the horizontal "red" line in the image below represents + 30 dBm.

(Click on images to enlarge)

Notes on this response:
  • Frequency range is 1 MHz to 100 MHz.
  • Internal RX Attenuator set to 0 dB of attenuation.
  • Overall again in the passband is about +33 dB (given that the horizontal red line represents +30 dB of gain).
  • By 50 MHz the gain has dropped by more than 40 dB.
  • The PicoFuse I added for front-end protection adds roughly 0.5 dB of loss (per measurements.  Note that is has about 6 ohms of resistance, measured at DC).

The image below shows the left side of the above response zoomed in.


Notes:
  • The horizontal red-line on the 8753C Network Analyzer represents +30 dBm.
  • At 1.8 MHz, the response is 30 dB down from the passband.
  • There is a slight amount of passband droop at the start of the passband, but it is only about 1 dB and in my opinion not significant.  

And here's that same zoomed-in response, but with 18 dB of "internal" receive attenuation added.


Looks good!  18 dB of attenuation, as expected.


Other Design Notes:  LTC6433 Testing:

Before Dick settled on the Push-Pull GALI-74 preamp, he tested some other ADC front-end designs.  One was the LTC6433.  Here are his notes on that device...

I took the opportunity to make a few measurements on an LTC 6433 demo board (DC2168a).

 It definitely has impressive odd order IMD performance:


But, even-order is equally important in this application --  the radio's "front end" is essentially "wide open" in that signals from 3 to 30 MHz get into the amplifier chain before the ADC.

Icom put banks of bandpass filters in line:
       15 discrete band-pass filters
          The RF Direct Sampling is protected by an array of bandpass filters.
           The signal passes through one of the fifteen bandpass filters, where signals outside the passband are rejected.

Well, that is not for me !!! 

Consequently, the even order IMD is important because strong out of band signals can mix (sum) to generate interference.

For this test, the generators output levels remained the same so that a 7 dBm PEP signal (full scale on ADC) was coming out of the LTC 6433. BUT, the signal frequencies were changed to 9 and 19 MHz so that the sum term would land at 28 MHz: 
  

As can be seen, the IMD2 term is loud and clear being 53+7 = 60 dB down from the PEP output.

Not bad, but not good, and no where near as nice as the IMD3 performance.

The main problem is the ADC Demo board  is a single ended 50 ohm input.  My solution to this was to build a push-pull class AB driver.

The driver, however, does not have enough gain (it is 10 dB) so it must be preceded with about 24 dB more gain.

Vlad Dvorkin's (KB9OLM)  recommendation of the GALI 74+  worked well BUT it also was single ended and had IMD2 performance that was not on par with its IMD3.  The solution: push-pull GALI 74s !  

The IMD2 and IMD3 of the overall front end are now comfortably better than 80 dB which is good enough for me! 


Other Design Notes:  Intrinsic Distortion, HP 8568B:

Before making IM3 and IM2 measurements, it is always useful to first check the distortion of the measurement system itself.  Here is an example of the intrinsic distortion of Dick's HP 8568B Spectrum Analyzer, with signal levels set to be equivalent to the FPGA SDR's ADC full-scale input level.

Note that some amount of attenuation (set via the 8568B's attenuator) is required to minimize the Spectrum Analyzer's distortion.

Here are Dick's notes:

As a check of the measurement instrumentation I ran IM3 and IM2 measurements on the 8586B. 

The synthesizers generating the two RF signals were each set to +4dBm out. There is 3dB loss in the combiner so this gives the desired 7 dBm PEP.

IM3:


IM2:


This can be improved:  IM2 drops essentially into the noise  with the 8568b attenuator set to 40 dB.  And some averaging is helpful:


In THEORY, it should drop 20dB, but theory has its limits.

The bottom line: The measurement capability is not a limiting factor. 


Mounting in Chassis:

The Preamp and ADC Driver dissipate a significant amount of power (about 2.5 watts), and so these boards are mounted on a copper heat-sink attached to the side rails of an HP chassis (that has been scavenged to house this radio):

(Click on images to enlarge)


The heat sink is a rectangle of 26 gauge copper sheet which itself is screwed tightly to the metal side-rails of the chassis.

The thermal connection between each board and the copper sheet is made via two copper pennies stacked and soldered together, with each 2-penny stack first soldered to the underside of one of the two boards and then to the copper sheet below.


Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion


Posts in this Series:

Part 1: Overview
Part 2: FPGA Modulation and Demodulation
Part 3: Interpolation and Decimation Filters
Part 5: Control Interface, Etc.


Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Thursday, May 25, 2017

An FPGA SDR HF Transceiver, Part 6 -- Schematics, Main Board

In this sixth blog post in my FPGA SDR Transceiver series, I will begin describing the radio's Hardware, specifically (in this post), the Main Board, which contains the FPGA, ADC, DAC, Audio Codec, and support circuitry.


(Part 5 of this series is here: Part 5)

But before I begin, let me again acknowledge Dick Benson, W1QG.  Dick is the father of this design, and although I've made some modifications to the FPGA logic, the underlying FPGA architecture and the vast majority of the Simulink implementation is Dick's.

A note regarding the schematics...

These schematics were drawn using the Lite version of Cadence's Orcad Capture.  This is the free version of the program, and it limits a schematic's number of nets to 75 and the number of parts to 60 (limitations which apply if you want to save the design, which I always do).

Because this radio design has many more nets and parts than the 75/60 limit specified by Cadence, I have broken the overall design into smaller "bite size" schematics, each  independent of the others and each drawn on a single A-size sheet.

But because I've broken up the design into smaller independent pieces, I can not use Capture's Design Rule Checker to check the overall design for design flaws.  Therefore, there is the possibility that errors have crept into the schematics.  So be aware!

A Note on Logic Levels:

A number of different logic families and devices are used in this radio.  I want to ensure that input logic thresholds and output logic drive levels are compatible with each other.  The spreadsheet below summarizes the different specifications:

(Click on image to enlarge)

Notes on Logic Levels:
  1. The Xilinx output voltages aren't high enough to meet the worst-case Arduino Input Level specification, so their levels will need to be shifted if driving Arduino inputs (this level-shifting is done in the Front Panel circuitry).
  2. 2N7000 devices make for simple I/O drivers (e.g. relay drivers, etc.)  But their worst-case Vgs is 3V.  This value is sufficient when driven with output levels from 5V devices (e.g. Arduino), but it is above worst-case Xilinx drive levels.  For this reason I will use bipolar transistors (rather than 2N7000 transistors) for I/O interfacing, when needed.
  3. The 74VCX245 transceiver is the output driver for the LTC DC918C ADC demo board.  It is powered by 2.5 VDC, and its outputs drive the Xilinx FPGA.

Now, let's look at the overall Block Diagram of the FPGA SDR radio...

FPGA SDR Block Diagram:

(Click on image to enlarge)

The Main Board, which is the subject of this blog post, incorporates the FPGA, RF ADC, RF DAC, Audio Codec, Speaker Amplifier, and various miscellaneous support and interface circuits.  It is the processing heart of the radio.

Notes on this block diagram:
  1. The T/R relay, when un-energized (OFF), shorts the receiver's input to ground, protecting the receiver input circuitry when the radio is off.
  2. Various interfaces are shown to external devices.  These interfaces will be explained further, below.
  3. All other circuitry not ON the Main Board will be described in future blog posts.
  4. Schematics and circuitry might change, as determined by design checkout.

Block Diagram, Main Board:

(Click on image to enlarge)

And below are some pictures of the Main Board in its Rev. A implementation:

Top Side

Bottom Side

And now, let's discuss the Main Board's hardware....

Hardware Design, Main Board:

Schematic, ADC Input:

(Click on image to enlarge)

Notes on ADC Input schematic:
  1. This radio uses a Linear Technology Demo Board (the DC918C, version C, incorporating an 80 MHz, 16-bit LTC2206 ADC) for the RF ADC.
  2. The DC918C's output drivers are 74LVX245 Buffers whose VCC is 2.46 volts (via an LT1763 LDO regulator).  Therefore, the maximum high-level voltage from the board to the Xilinx inputs is about 2.26 volts (assuming 100uA worse-case output current -- this voltage falls as output current increases).  With drive current at about 6 mA, the output voltage level is just within Xilinx input threshold specification, with the margin vanishingly small if using the Xilinx LVCMOS33 spec, but better with the LVCMOS25 spec.
  3. 12 VDC power comes in to the radio on this page.  It is converted down to 5V using a simple LM2576 buck regulator, and it is this 5V power buss which sources power for the 3.3V LDO regulators used throughout this design.
For reference, here is the schematic of the LTC DC918C ADC Demo board that Dick and I use in our radios.  The table in the lower left-hand corner specifies component values for the different board versions, including the -C version used by us:

(Click on image to enlarge)

Notes on the DC918C ADC Demo Board:
  1. Dick and I use the DC918C-C version of the DC918C Demo Board (80 MHz LTC2206).  No modifications were made to this board.
  2. Schematics and other design files for the DC918C-C board can be found at the Linear Technology site: http://www.linear.com/solutions/3274
  3. LTC2206 Documentation can be found here: http://www.linear.com/product/LTC2206
  4. The DC918C-C's on-board jumpers are set as follows:
    • JP1:  Set to GND, not OVP.
    • JP2 (SENSE):  Set to VDD, not OPEN.
    • JP3 (PGA):  Set to VDD, not GND.
    • JP4 (RAND):  Set to GND, not VDD.
    • JP5 (SHDN):  Set to GND, not VDD.
    • JP6 (DITH):  Set to GND, not VDD.

Schematic, Clock and Misc.:

(Click on image to enlarge)

Notes on Clock and Misc.:
  1. The 80 MHz clock source is a Conner-Winfield TCXO (available from Digikey), part number TB522-080.0M.  (LVCMOS outputs, 3.3Vdc).
  2. This TCXO drives a 74AC04 inverter whose input has been biased to mid-scale DC (1.65V) and which is AC-coupled to the TXCO output.  This inverter, in turn drives other 'AC04 inverters which act as clock drivers, so that the FPGA clock, the ADC clock, and the DAC clock are driven independently.  Thus, there is no clock daisy-chaining.
  3. R11 and R10 slightly roll off the clock edges to reduce ringing.
  4. J1 is the 26-pin header to connect the radio's Front Panel to the Main Board.
  5. Note that because the Front Panel's Arduino's output levels are referenced to the Arduino's 5V power, R5 and R6 drop the Arduino output voltages down to a level more compatible with the Xilinx input levels.
  6. R9 and C14 filter (and scale) the S-Meter PWM signal.  Note that the meter is 1mA Full Scale.
  7. Q1 (open-collector inverter) can be used by the Front Panel (Arduino) to Reset the FPGA.  For example, this is used if the Command Interface gets out of sync.
  8. The oscillator and 74AC04 are powered by the same 3.3V regulator used to power the LTC 918C-C ADC board.  (This regulator also powers the Audio Codec).

Schematic, Xilinx FPGA Board:

(Click on image to enlarge)

Notes on Xilinx FPGA Board:
  1. Dick and I use a Waveshare Core3S500E Xilinx Development Board to simplify the FPGA hardware implementation (no need to solder an FPGA!).
  2. This schematic page defines which pins of the Waveshare Core3S500E board are used in this radio.
  3. I disabled the on-board 50 MHz oscillator by grounding its output-enable pin (pin 1), thus allowing the external 80 MHz clock to be connected to this oscillator's pin 3.  (Note that pin 1 in the Waveshore partial-schematic, below, is simply called "NC".  It actually is the oscillator's OE pin.)
  4. FPGA outputs TX_ATTEN_0 and TX_ATTEN_1 are not yet used in the design.  I've included them in case I would like some way to change TX gain apart from adjusting the TX_Level within the FPGA.  For example, these two bits could select different values for the DAC's full-scale current resistor.
  5. My modifications to this board are described below:
Mods to Waveshare Core3S500E Xilinx Core Board:

(Click on image to enlarge)


Notes on Mods to the Waveshare Core3S500E:
  1. Additional information on the Waveshare Core3S500E board can be found here: http://www.waveshare.com/wiki/Core3S500E

Schematic, DAC Out:

(Click on image to enlarge)

Notes on DAC Output:
  1. The DAC is an AD9744 14-bid ADC
  2. I use a separate 3.3V regulator for the DAC (to minimize possible noise injection into the DAC via its VCC pin if this regulator were also powering other devices).
  3. R1 sets the full-scale output current.  With 2K ohms, full-scale current is 19.2 mA +/-5%, assuming R1 is 1%, given the spec'd range of VREFIO.
  4. IFS = 32*VREFIO/R1 = 32*1.2/R1.

Schematic, Audio Codec:

(Click on image to enlarge)

Notes on Audio Codec:
  1. The Audio Codec is an AKM AK4554 16-bit stereo audio codec.
  2. FPGA outputs driving this Codec are lightly filtered (e.g. R4/C17), to round off edges and thus lower harmonic energy (just in case they might be picked up by the receiver).  Note -- strictly speaking, these 1-pole filters might not be needed in this design, but I got into the habit of using them long ago to help ensure that products I designed met EN61000 EMC standards.  You'll see me use this technique throughout this design.
  3. All inputs (or outputs) to/from the outside world (e.g. Mic In, Line In, and Codec Right Out) are protected with TVS devices and series-resistors at the inputs (the latter to limit transient current).
  4. R1 (33K) sets the voltage gain of U2 (the Speaker Amplifier, a TPA0211 device) to 3.8 (= 125K/33K), which ensures that at the maximum Codec output (1.98 Vpp), the amplifier's drive into a 4-ohm speaker load will be about 1.8 watts RMS -- just below 2 watts, above which amplifier distortion increases significantly, per the TPA0211 datasheet.
  5. J4 may or may not be used in the final design.  If not used, I jumper J5 pin 3 to J5 pin 4.
  6. The primary function of C11 (510 pF) is to shunt RF (to hopefully minimize RF susceptibility).
  7. This design originally used a TI PCM3008 codec.  But the TI codec has greater out-of-band noise compared to the AK4554 (which is pin-for-pin compatible with the PCM3008), as the following image demonstrates:
(Click on image to enlarge)

Schematic, Interconnects 1:

(Click on image to enlarge)

Notes on Interconnects 1:
  1. A separate 3.3V regulator is used to power the board's various interface circuitry (on this schematic page and the next 3 "Interconnects" pages).
  2. External I/O: EXT. IN and EXT. OUT usage is yet to-be-defined.  I've included this I/O in the design "just in case" I find a need for it later.
  3. EXT_IN should not be driven higher than 3.3V -- TVS1 will protect it from over-voltage (current-limited by R7).  And in the event of a large, positive-going transient event, D7 should prevent Q2's base-emitter junction from being damaged by an accidentally high reverse-bias Vbe voltage. (And note that EXT. IN will source power (3.3V dropped by Q2's Vbe, D2, and R7, so must ensure that devices attached to this pin will not be harmed by this current when they are powered off).
  4. Controls for an external Receive Attenuator are included.  This attenuator might be a Mini-Circuits DAT-31A-SP+ Digital Attenuator, but it could be something else, as long as I can set attenuation with 3 bits.
  5. I've included an EXT. PA T/R relay-closure output for controlling external power amplifiers such as my SB-220 or AL-811.

Schematic, Interconnects 2:

(Click on image to enlarge)

Notes on Interconnects 2:
  1. This page contains an interface for communicating with my Automatic Antenna Tuner.  Thbis is a bit like putting the cart before the horse, because I don't have a corresponding interface in the Tuner.  Never the less, someday there might be one!  And in anticipation of that event I thought I'd add the circuitry here.
  2. The Interface is pretty much self explanatory.  The signals to the outside world have TVS with current-limiting protection.  And RF bypassing with small caps.
  3. Also, output filtering for three FPGA outputs is shown on this page -- these three filters were originally on the FPGA schematic page, but their inclusion there meant that the schematic exceeded the Orcad Lite's limits on nets/parts, so I moved them here.

Schematic, Interconnects 3:

(Click on image to enlarge)

Notes on Interconnects 3:
  1. I hope to incorporate a Flex-radio SDR-1000 PA module that I have into this radio to give it 100 watts out.  Details are sketchy at the moment -- this PA might be mounted inside this radio's chassis, or it might be mounted in a separate case (so that it could be used for other purposes when not used for this radio.  The important point is -- nothing is yet finalized!  If the PA ends up in a separate case, I will probably use a 25-pin D-connector to connect that chassis to this radio  -- using ribbon cable between the two units with ground between each signal will help reduce EMI susceptibility.  Thus, the reason for J3.
  2. Assuming the SDR-1000 PA performs as I hope it will, I will describe in a later post how it connects to this radio.
  3. Open-collector drivers communicating between this radio and the PA provide a very simple interface between boards with different logic voltages (e.g. the radio's 3.3V digital power versus the PA's 5V digital power) -- no level-shifting required.
  4. ESD protection of the signals driven by the ULN2003A is provided, for positive-going pulses, by TVS2, connected to U1's internal clamping diodes.  Although I've never tried ESD protection this way, it seems to me it should work, and it saves parts, as I don't need a TVS device for each line. Negative-going pulses are clamped by internal clamp diodes (within the ULN2003) between the output pins and ground.

Schematic, Interconnects 4:

(Click on image to enlarge)

Notes on Interconnects 4:
  1. A future project of mine is a 500 watt external PA.  This interface would allow the FPGA SDR radio to set automatically the PA's output filters, etc.  Note this interface's similarity to the SDR-1000 interface, above.
  2. I've added an extra PA Filter-selection signal (nFilt_F3), in case I need to specify separate, rather than combined, filters (e.g. the SDR-1000 PA combines 10 and 12 meters into a common filter, but I might find that I need to separate these filters into two separate filters, rather than one combined filter, in the 500 watt PA).
  3. Due to Orcad Lite's net and part limitations, the SW1 and SW2 are shown on this page rather than on the FPGA page.

Construction Notes:

This board was built on a piece of scrap double-sided FR4 PCB stock.  Very handy, and it provides an excellent ground plane.  I cut holes in it to mount the FPGA board so that I could easily access both sides of this board, as well as to mount an Electroboard prototyping board with the AD9744 DAC soldered to it.  (I also use one of their prototyping boards to mount the PCM3008 codec, but I did not cut a hole into the main board -- instead, this prototyping board is soldered to the top ground plane of the main board).

For mounting small parts, I often used small rectangles I had cut from a larger BusBoard Prototyping Systems prototyping board.  These are great for mounting small SMD devices,  relays, and even ULN2003A DIP ICs.


And at times I also carved pads out of the copper plane on either side of the main PCB (depending upon which side it made sense to mount the components), using a Dremel tool and a 30 degree, 0.1mm Tip Diameter Conical Engravers Cutter V-bit.  You can see an example of this, above, for the 3.3V LDO regulator used to power the interface circuitry.


That's it for this blog post!


Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion


Posts in this Series:

Part 1: Overview
Part 2: FPGA Modulation and Demodulation
Part 3: Interpolation and Decimation Filters
Part 5: Control Interface, Etc.


Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.