Friday, February 17, 2017

SDR Notes: Weaver Modulation and Demodulation


There are two techniques commonly used for modulating and demodulating SSB signals:  filtering out the unwanted sideband with a filter, and cancelling the unwanted sideband by using a phasing technique that includes shifting the audio frequencies by 90 degrees.

In 1956 Donald Weaver published a third method in the Proceedings of the IRE ("A Third Method of Generating and Detecting Single Side Band Signals", Dec. 1956).



Although this technique has now been around for more than 50 years, it was never widely utilized in commercial SSB products.

This lack of adoption by commercial manufacturers might be, in part, due to the requirements placed upon the analog design and implementation of a Weaver Modulator/Demodulator -- the low-pass filters should be matched, as any phase errors between the two will result in appearance of the opposite, unwanted sideband along with the desired sideband.  And imbalance or DC offset can cause the low frequency oscillator to "bleed through" into the audio passband.

Given these requirements, it is not too surprising that manufacturers preferred, for example, the straight-forward technique of simply filtering out the unwanted sideband with a crystal or mechanical filter at the radio's IF frequency.

But what might be difficult to implement in the analog domain becomes trivial in the digital domain -- filters are exactly matched, DC offsets can be eliminated, and thus Weaver modulation and demodulation become an excellent choice for implementation in a digital transceiver.

There is an additional benefit, too, in using Weaver's technique versus the phasing technique (in which the 90 degree audio phase shift is implemented in the latter via a Hilbert Transform).

And that benefit is this:  Weaver modulation allows TX AGC (i.e. ALC) to limit the maximum TX signal in the audio stage, prior to modulation.

In other words, an AGC stage in the transmit audio path can ensure that the Audio level never exceeds a fixed maximum peak-to-peak level, and this maximum level will be maintained throughout the successive modulation and filtering chains.

On the other hand, in a digital radio utilizing the phasing (i.e. Hilbert Transform) technique to generate SSB, the ALC function must be performed after the  modulator's 90 degree phase shift of the audio signals (i.e. in the I/Q domain) because this phase-shift can change signal levels dramatically (an example as to why this is a problem can be found here, from some 2011 experiments of mine).

Thus, the phasing-technique can complicate a transceiver's design, especially if one is trying to optimize resource utilization by sharing functionality (such as AGC) between TX and RX functions.

Now let's take a closer look at Weaver's technique...


Weaver Modulation:

Here's is the block diagram for Weaver's Modulator, as described in U.S. Patent 2,928,055:


And here is its implementation:



Three comments:

1.  The block diagram shows sine and cosine signals driving the balanced modulators.  Note that these signals are implemented in the schematic with two oscillators:  one at the AF frequency and one at the RF frequency, and these oscillators are each shifted + or - 45 degrees (depending upon which "branch" (upper or lower) of the modulator they drive) to achieve the requisite 90 degree phase shift between upper and lower branches.

2. Assuming the phase of the output transformers sum the signals from the two branches rather than subtract, the modulator above generates USB.  To generate LSB, either the phase of the audio into the "sine" branch must be inverted, or the RF output from the "sine" branch must be inverted.

3.  With respect to I and Q, the branch mixed with the cosine signals would be the I (In-phase) channel, while the branch mixed with the sine signals would be the Q (Quadrature) channel.


Weaver Modulator Theory:

Let's look at how the operation of a Weaver Modulator is typically described.  From a 73 Magazine article (Feb. 1977), here is a block diagram very similar to Weaver's original:


And here is its associated spectrum diagram showing the step-by-step conversion from Audio to USB:


Note that the outputs of Balanced Modulators A2 and B2 each contain two versions of the shifted audio spectrum.  The spectrum of Modulator A2's output has two "positive" spectrums, one whose frequencies are reversed from the other.  The spectrum of Modulator B2's output also has two spectrums, one with reversed frequencies from the other, but in addition to the reversed frequencies one also has reversed amplitudes ("upside-down").

If these outputs are then added, spectrums that have a common frequency orientation and identical amplitudes will add, while spectrums with a common frequency orientation but reversed amplitudes will cancel (sum to zero), thus cancelling one of the sidebands.

I was curious how the Q channel (i.e. modulator B2 in the block diagram, above) inverted the spectrum amplitude, so I thought I'd look into circuit operation a bit more deeply.  As a visual representation I came up with this diagram:


This diagram represents a USB modulator.  Note that every time a signal is multiplied by a sine, its phase shifts by 90 degrees (I represent this as a 90 degree rotation), and this  phase shift is key to understanding how the "upside-down" spectrum is created.

In other words, if one were to think of Weaver Modulator operation in terms of sines and cosines, where the Audio input is a cosine signal, then, the first Q mixer's output would consist solely of sines:


The second Q mixer would convert these sines back to cosines:

(Equations from here)

But note!  Now there is a negative sign in front of the final cosine term.  If you were to write the equations of signal transformation for both I and Q branches, from audio to RF, and then sum them (per the block diagram), it is this negative sign result in the Q channel that causes the cancellation of one sideband.

(Personally, I prefer my visual representation over the equations, as the latter, as one expands them, can quickly become cumbersome.)

Here's a similar diagram for LSB generation:




Note that the LSB generator inverts the Audio signal in the Q path, prior to the first Q-channel mixer.  To create LSB, this inversion can either be at the beginning of the Q-channel path (prior to the first Q-channel mixer, as shown above), or at the end of the Q-channel path (after the second Q-channel mixer, but prior to the final adder).

The diagrams above, representing how a Weaver Modulator might be implemented in an FPGA, can look daunting.  For a different approach, let's look at Weaver Modulation from the perspective of "Complex" signals, which allows us to examine Weaver Modulation without the complication of spectrums folding back upon themselves:

USB Generation:


And LSB Generation:


Notes:

1.  The signs of the oscillator frequencies for the two final multipliers have been swapped (negative for positive, positive for negative) in the LSB version, compared to the USB version.

2.  The Complex Conjugate of a complex exponential function simply changes the sign of that function's frequency, from positive to negative, or from negative to positive, as shown below:


(For a very useful tutorial on Complex signals, go here).

Forward to demodulation!


Weaver Demodulation:

(This will be a very short section.)

From Weaver's Patent:


Looks very similar to the modulator, doesn't it?

Because there are no phase inversions in the diagram above of  RF prior to the first modulators or Audio following the final modulators, then this demodulator would demodulate a USB signal.

To demodulate an LSB signal, instead of adding top ("I") and bottom (Q") branches to create audio, you would instead subtract the bottom branch (Q) from the top branch (I).

As you can see, demodulation is essentially just the reverse of the modulation process.  And with that, I now end my discussion!


Resources:

"A Third Method of Generation and Detection of Single-Sideband Signals," Weaver, Proceedings of the IRE, Dec., 1956.  The original article!
Weaver's Patent 2928055
A 9 MHz Digital SSB Modulator, IV3NWV
AN1981, Philips.  Contains description of Weaver Modulator and Demodulator.
SSB Demodulation, Pandora SDR.  A nice visual on Weaver Demodulation.
"The Third Method of S.S.B.", Wright, W1PNB, QST, Sept., 1957
"SSB:  The Third Method," Wilson, WB0JXY/0, 73 Magazine, Feb., 1977

Quadrature Signals:  Complex, but not Complicated, Richard Lyons


Standard Caveat:

I might have made a mistake in my designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Monday, February 13, 2017

An FPGA SDR HF Transceiver, Part 1 -- An Overview

Introduction:

This post is the first in a planned series of posts describing an FPGA SDR HF transceiver.

This series will describe both the FPGA internal logic and the external hardware used to create a fully functioning, stand-alone HF transceiver.  No PC is required to drive it (after the FPGA's configuration EEPROM has been programmed, of course).

Audio and RF are digitized with Analog-to-Digital Converters (ADCs) and provide the digitized signal inputs for a single FPGA (Xilinx XC3S500E).  In turn, Digital-to-Analog Converters (DACs) convert the FPGA's digital outputs back to analog RF and Audio.


Dick Benson, W1QG, has designed this radio's FPGA logic using Simulink software (from The Mathworks, Inc, and it is this software which defines the software part of "SDR" in this design), based upon an earlier CW/SSB Transceiver design of his that used both an FPGA and a DSP (and which, if the link still works, is described here).

This new design uses a single FPGA and no DSP.  In Dick's own words, enhancements to that earlier design include:

1)   Elimination of DC offset in the processing chain which causes a tone at the BFO freq. with very low RX input levels.
2)   Loadable Information (i.e. passband) Filters.
3)  Hang AGC.
4)  Read back of FPGA Version.  This has saved my butt more than once!
5)  TX Demodulated Signal Monitor.
6)  Loadable TX Audio EQ Filter.
7)  Loadable RX Audio EQ Filter.
8)  AM Modulation and Demodulation.
9)  TX Audio Monitor:  Monitor, during transmit, how the TX Audio EQ Filter and the Information Filter affect the quality of the Transmit Audio signal.

I also made a few enhancements of my own to Dick's design:

1)  Modified the AGC subsystem to, among other things, allow the user to set Maximum AGC gains for RX and TX paths.
2)  Added the ability to bypass the AGC "Attack" Filter.  (More on the reasons for this when I discuss the AGC subsystem in a later post).
3)  Added GPIO pins to the FPGA so that the Control Panel software can, for example, drive local relays via the FPGA, rather than requiring an additional cable be routed from the Control Panel.

In addition to the three listed above, there are a few other small differences between our two designs.  I'll mention these when we arrive at them in later posts.

To get a taste of the design, let's first take a look the Hardware which makes up the radio's core.

Hardware Overview:

The radio's core consists of four ICs, three to convert between the analog and digital realms, and the fourth to perform all radio processing functions digitally (e.g. passband filtering, demodulation/modulation, AGC, etc).  These four ICs are:
  • A single Xilinx XC3S500E FPGA
  • An LTC2206CUK 16-bit, 80 MHz ADC
  • An AD9744 14-bit RF DAC
  • A TI PCM3008 Audio Codec
Here is a block diagram of the radio core:

(Click on image to enlarge)

(In the diagram above /OVLD is an "overload" signal, and it is used to inform the operator if signals are too high at (for example) the RF or Audio ADC inputs.)


To simplify the design, Dick and I use pre-existing development boards for both the FPGA and the ADC.

The FPGA board is Waveshare's Core3S500E development board (circa $30):

The LTC2206 ADC is installed upon an LTC DC918C-C development board.  It is available from Digikey, but note -- it is quite expensive!


Here's my version of this radio-core:


And here is Dick's breadboard, with additional bells and whistles:



How might this radio-core be incorporated into a transceiver design?  Here is one possibility:

(Click on image to enlarge)

Note that because the RF ADC is clocked at 80 MHz, incoming RF must be frequency-limited to 40 MHz or below.

Future posts will add further detail to both the Core and Transceiver hardware, including schematics.


A quick mention of hardware tools:

In addition to the usual suite of hardware test equipment, one needs a way to program the FPGA and some way to control it (for development and debug) via Dick's 4-wire serial Command Interface.

To program the FPGA I use Waveshare's Platform Cable USB:


And to control the radio I built a simplified Control Panel (using an Arduino Nano):


Dick's Control Panel is similar, but he uses a PIC processor on a PIC development board.  You can see both the board and the controls (the latter mounted on Plexiglas) on his radio breadboard, below:



Now let's take a quick look at the FPGA internal functions...

FPGA Functional Overview:

The FPGA contains both Receive and Transmit Functions, as well as other functions such as the Command Interface.  In short, there is quite a bit of functionality crammed into the single FPGA (in fact, its number of "occupied slices" stands at about 95% -- not much more can be squeezed in!)

Let's first look at the Receive side.  Here is a functional block diagram of the Receivers:

(Click on image to enlarge)

Notes on these receiver function blocks:
  • The digitized RF ADC signal comes into the FPGA as a "Real" (i.e. not Complex) 16-bit, two's complement value.
  • The High Frequency DDS down-converts this signal to an intermediate frequency in Complex (I/Q) format.  Note that the data, although down-converted, is still running at an 80 MHz clock rate.
  • The Decimation Filter filters and converts the Mixer data (running at at 80 MHz), down to data rate of 9,765.625 Hz (a Decimation ratio of 8192).
  • CW and SSB are demodulated with a Weaver Demodulator, which consists, in part, of the Information Filter and the Low Frequency DDS and Mixers.  The Weaver Modulator and Demodulator are particularly straight-forward to implement in an FPGA.  
  • The Information Filter is a low-pass filter than, when combined with the Weaver Demodulator (or Modulator) represents a passband filter whose passband is twice the bandwidth of the low-pass filter.  It also determines the AM signal's audio bandwidth -- each sideband of the AM signal will have a bandwidth equal to the passband of the low-pass filter.  This filter is a 128-tap symmetric FIR whose 64 coefficients can be loaded via the radio core's Command Interface (e.g. from my Arduino or from Dick's PIC), thus, the user can invoke any number of custom passbands.
  • The AM Demodulator consists of an Envelope Detector.  Note that for AM Demodulation the IF frequency is 0 Hz and the Weaver Demodulator is not used.
  • The AGC block amplifies the converted signal so that its peak amplitude is essentially between +/- 1.0 (well, actually +0.9999../-1.0), as represented by 16-bit signed, two's complement values, whose decimal point is at bit 15.  This AGC block has two values of decay, Fast and Slow, and it has a programmable "hang" (more details on AGC will follow in a later post).
  • The RX EQ filter can serve a variety of purposes.  It can filter out low level "hiss" noise (quantization noise amplified by the AGC when it boosts low-level signals).  It can remove key-clicks from the local side-tone signal.  It can be used as an EQ filter, etc.
  • Audio volume can be controlled digitally (attenuated) with the RX Level value.
  • The 16-bit two's complement digital audio (representing max values of +/-1.0) is converted into a serial stream for the PCM3008 Audio Codec.
  • Note that during Transmit, this codec will also convert the TX Monitor Audio signal to an analog output, thus allowing the operator to monitor how the transmitter's EQ and Information Filter (i.e. passband filter) affect the quality of the transmitted audio.

Now let's look at the Transmit side.  Here is a block diagram of the Transmitter:

(Click on image to enlarge)

Notes on these transmitter function blocks:
  • The serial data from the PCM3008 Audio codec (in 16-bit, two's complement format) is first converted to 16-bit parallel data.  Because the codec is stereo, this data can actually be from two sources: either a Mic or from, for example, a Line-Level audio source).
  • This data then passes through an TX EQ block to transform its spectrum, should that be required.  The EQ's filter coefficients can be downloaded from the Control Panel via the FPGA's Command Interface.
  • The AGC block amplifies the audio and ensures that its max level is no greater than +/- 1.0 (when represented as a signed two-compliment 16-bit number whose decimal point is at bit 15).
  • At this point AM audio can be generated by adding a DC offset (Carrier Level) to the Audio signal.
  • The AM or SSB (or CW) audio is then attenuated via the TX Level value.  It is this level that controls TX output power.
  • The Audio then drives a Weaver Modulator, consisting, in part, of the DDS Low Frequency LO, two mixers (to create a Complex signal), and the Information Filter (which determines the bandwidth of the transmitted audio). Note that in AM mode the DDS Low Frequency LO is set to 0 Hz.
  • The Interpolation Filter converts (by interpolation) the Weaver Modulator's Complex (I/Q) output from its 9,765.625 Hz Audio sample rate to a complex signal whose sample rate is 80 MHz.
  • The complex output of the Interpolation filter is then mixed with the DDS High Frequency LO and up-converted to the desired RF frequency, creating a real, 14-bit, two's complement signal at an 80 MHz clock rate for the AD9744 DAC.  It is this High Frequency LO (and the summing stage following it) that, in CW and SSB modes, completes the Weaver Modulator.
  • TX Monitor Audio allows the operator, during transmit, to monitor how the TX EQ and Information Filter functions affect the quality of the transmitted audio.

To incorporate both the transmitter and receiver into a single FPGA, some sharing of functions is required.  The TX and RX functions share the following functional blocks:
  • High Frequency DDS oscillator and I/Q mixers.
  • Low Frequency DDS oscillator and I/Q mixers.
  • AGC (increase RX signal level, and level the Mic signal).
The other main function block within the FPGA is the Command Interface block, which allows the FPGA to be controlled by an external processor, such as a PIC or Arduino.  I will discuss this block in a future post.

Now, let's take a look at what software tools are needed for FPGA development...


FPGA Development Software Overview:

As I mentioned above, Dick developed the FPGA's logic using The MathWork's Simulink program.

Simulink not only simplifies the design process by allowing the designer to create a design using functional blocks (much like a schematic) in lieu of typing in a design with either VHDL or Verilog, but it also provides a powerful ability to simulate a design prior to implementation.  Ideas can be tested via simulation, and, if one has MatLab's "Fixed-Point Designer," then the actual effects of fixed-point arithmetic can be verified in a designs.

However, to create a design that can be downloaded into a Xilinx FPGA, you will need to use Xilinx "blocks" in the Simulink model, and these blocks are contained within the Xilinx "Blockset." This blockset is only available with the Xilinx System Generator software. Below is Xilinx's description of the System Generator:
System Generator is a DSP design tool from Xilinx that enables the use of the MathWorks model-based Simulink® design environment for FPGA design. Previous experience with Xilinx FPGAs or RTL design methodologies are not required when using System Generator. Designs are captured in the DSP friendly Simulink modeling environment using a Xilinx specific blockset. The System Generator design can then be imported into a Vivado IDE project using the IP Catalog.
Dick has the tools and did the majority of the design, and then we incorporated my changes into a revision for me.
An important caveat!  To create an FPGA using Simulink and the Xilinx System Generator, the version of MatLab (and Simulink) must be compatible with the version of Xilinx System Generator.  If you do not already have the tools and are considering their purchase, verify first their compatibility!
For those who do not have the these tools (and do not contemplate their purchase) but have the interest, skill, and time to implement an FPGA radio, they could use one of the inexpensive (if not free) HDL compilers and try to recreate the design in HDL from the Simulink model that I will present in this series of posts.

And so I will try to include as much detail of the FPGA design as possible, so that those who might want to recreate Dick's design in HDL will have a running start at doing that.  (Note: some Xilinx blocks, such as CIC and DDS blocks, contain Xilinx Intellectual Property, and, apart from a definition of high-level parameters, cannot be delved into).


Now let's discuss some features of a typical Xilinx Simulink Model, so that you might better understand what you will see later...

Notes on Xilinx Simulink Models:

Let's take a look at an example of one of the Simulink Subsystem blocks in the FPGA Simulink Model to get an idea of Xilinx/Simulink design nomenclature.

Here is the Clock Divider subsystem, which divides down the 80 MHz FPGA clock to 20, 10, and 5 MHz (for external applications, such as locking the radio-core's 80 MHz oscillator to an external time-base, as Dick has done).

(Click on image to enlarge)

In this image please note:
  • The blocks with a light-blue fill and a stylized "X" white shadow within them are Xilinx blocks available only through the Xilinx Blockset provided via their System Generator.
  • The output definition of the counter, UFix_4_0, means that this data is 4 bits wide, that these four bits represent an unsigned number (the U suffix), that this number is fixed-point (the Fix), and that the fixed-point number's Decimal Point is at bit 0. Thus, this example represents values between 0 and 15. 
  • In other instances, such as those blocks dealing with actual RF or audio signals, data will be passed as signed two's complement numbers.  For example, you might see a data format of Fix_16_15.  Note the absence of a U suffix -- the data is therefore signed two's complement.  And 16_15 means that the data word is 16 bits wide, and that it has a Decimal Point at bit 15.  So, in this case, values would range between +0.999...(i.e. the highest possible positive value, as represented by 0x7FFF) and -1.0.  (In other words, the 65,536 values represented by the 16 bit word would range, essentially, between +1.0 and -1.0.)
  • The "z-1" label in some blocks means that there is a register delay within this block (1 clock delay for z-1, but this delay could be longer, e.g. z-25 would represent a 25 clock delay within a block).
  • The "++" label within the counter means that it is an UP counter.  
If you could click on the counter block in the image above, you would see its parameter window:

(Click on image to enlarge)

Note that the last entry shows the counter's Sample Period as "1/Fs".  Fs is the frequency of the FPGA's system clock, which is 80 MHz in this application.

Another useful block, found in the subsystem above, is the "Slice" block.  The Slice block allows one to take a "slice" of data from a multi-bit wide data word.  For example, in the Clock Divider, I want to use three of the counter's output bits to create 20, 10, and 5 MHz clocks.  I do this by taking three 1-bit wide slices, each slice being a different bit of the counter's output.

If I click on the "Slice1" block, I will see the window below, which describes this slice as 1 bit wide and the MSB of the counter's 4-bit output (i.e. the 1-bit slice has a "0" offset from the top-bit of the value being sliced):

(Click on image to enlarge)

Per the image above, slices can also be referenced from the LSB bit location, and they can be of widths other than 1.

By the way, there is a complementary function to the Slice function which allows one to combine bits (or words) into larger words.  This function called "Concat" which allows you to concatenate any number of bits to form a wider word.

Here's another Simulink/Xilinx example.  Let's take a quick look at it.


Notes on this image:

1.  Note the "Bool" labels on some interconnects.  This stands for "Boolean", and it represents a logic value, rather than a signed/unsigned numerical value.

2.  You can have Constants.  These can represent multi-bit (or single-bit) signed/unsigned words, or Boolean values.

3.  This system takes data from one clock domain (whose clock is slower by a factor of 16), up-samples that data to the higher clock rate (this is the clock rate that the counter at the left is clocked at), and then down-samples it back to the slower clock rate.


OK, that was a very quick overview of the Simulink model's Xilinx nomenclature!  Finally, let's take a look at the Top Level of the FPGA Simulink Model...


Top Level of the FPGA Simulink Model:

Here's the Top Level Simulink Model of my version (rev. 1.0) of the FPGA:

(Click on image to enlarge)

Notes regarding this diagram:
"Subsystem" blocks are the blocks with white fill, such as the Serial Interface1 block, or the Audio_and_Mode_Control block.  Clicking on one of these blocks would open that subsystem into a new window to reveal the circuitry within that subsystem.  For example, if one were to click on the Clock_Divider subsystem block in the Simulink model, it would open up to reveal the image below (which you've already seen, above):



Delving deeper into the Top Level...

In the upper left hand corner of the Model's Top Level you see this:

(Click on image to enlarge)

In the image above:
You would click on the "System Generator" icon (which is one of the blocks available in the Xilinx Blockset) to generate a .XISE file.  The .XISE file is then transformed into a .BIT file by the Xilinx ISE Design Suite  (now the Vivado tool?).  The .BIT file, in turn, can be converted (using the Xilinx iMPACT program) into a .MCS file for loading into the FPGA board's EEPROM).
The icon labeled "DOC Text" is a document file in which I track my FPGA revision changes.
The Xilinx block named "Versionx10" is actually a "Constant" block (whose label has been renamed for convenience).  In this revision, it contains the value 10, representing a revision level of 1.0 (a value of 11 would represent a revision level of 1.1)
The yellow In blocks represent either individual FPGA input pins (in the case of the nRESET input), or groups of FPGA input pins (e.g. 16 pins for the hf_adc In block).  Clicking on this block in the actual model would bring up a window showing which actual FPGA pin(s) are assigned to an In block.
Note that there are similar yellow block for FPGA output pins.  They are labeled Out.

I will note here, too, that not all FPGA I/O are shown on this top-level of the model (to keep Top Level complexity to a reasonable level).  Quite a few of the other I/O pins are buried within various subsystem blocks.

(You will note a number of Subsystem blogs, shown in  the image above, that are external to the FPGA itself (i.e. they drive FPGA input pins, etc.), such as the "RF Source" Subsystem and the other blocks connected to it.  Dick uses these to test/check his Simulink model, and you who are familiar with Simulink will know what they are.  I would like to be more informative, but I'm not (at this time) a Simulink user.)


That's my very brief description of Simulink's Xilinx nomenclature.  I'll add more details in future posts, as needed, when we examine more closely the Simulink Model.

More to follow in later posts...!


Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion


Additional Resources:

"A Third Method of Generation and Detection of Single-Sideband Signals," Weaver, Proceedings of the IRE, Dec., 1956.  The original article!
Weaver's Patent 2928055
A 9 MHz Digital SSB Modulator, IV3NWV, contains an excellent depiction of how a Weaver Modulator filters and translates an Audio signal.
AN1981, Philips.  Contains description of Weaver Modulator and Demodulator.
SSB Demodulation, Pandora SDR.  A nice visual on Weaver Demodulation.
"The Third Method of S.S.B.", Wright, W1PNB, QST, Sept., 1957
"SSB:  The Third Method," Wilson, WB0JXY/0, 73 Magazine, Feb., 1977


Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

Sunday, January 29, 2017

An FPGA SDR HF Transceiver, Part 1

If you've arrived here, you've arrived at an old post that has been superseded!

To go to the new FPGA SDR Transceiver posts, please click


(Thanks!  Jeff, K6JCA)

Tuesday, October 18, 2016

SDR Notes: The Mixer Mathematics of Digital Down Conversion

(This post originally started as notes to myself, placed here so that I would not lose or forget them.)

The Digital Down Converter (DDC) is a basic block of FPGA-implemented SDR radios.  Per Wikipedia:
A digital down-converter (DDC) converts a digitized, band limited signal to a lower frequency signal at a lower sampling rate in order to simplify the subsequent radio stages. 
Below is an illustration of a DDC stage (don't worry about the math -- it will be explained later in this post):

(Click on image to enlarge)

Note that, for demonstration purposes, the equations assume a simple cosine as the input signal.

This post will look at the math involved in the Mixer.  I will leave the low-pass filter and sample-rate conversion for later posts.


First, some basics...

Basic Down-Conversion Mixing:

Historically, down-conversion has been done in the analog domain with a "real" oscillator signal (e.g. cos(ωot)).  Let's first look at this type of basic mixer before tackling mixing in the Digital (and Complex) domain.

For demonstration purposes, I'll simplify the receive-signal to be a just simple cosine signal at a single frequency:  cos(ωit).


This mixer's math is straightforward.  Let the output of the mixer be y(t).

y(t) = cos(ωit)*cos(ωot)

We can use Trigonometric identities to express this equation in terms of sums and differences of frequencies:

y(t) = (cos((ωi−ωo)t))/2 + (cos((ωio)t))/2

But this basic form of mixing has a problem if one would like to down-convert an incoming RF signal directly to base-band:  both the desired signal and its image will appear in the base-band spectrum (which, for the typical shortwave receiver, is the audio spectrum we want to hear).

This type of conversion is known as "Direct Conversion."  For an example, see Rick Campbell's R1 receiver.

Visually, here's how the frequencies shift, shown as a single-sided spectrum (which one would see if one did a "Trigonometric" Fourier Transform on the RF input.  Refer to equation 27 in this paper by Robert Marcus for more detail)::


Note the overlap of the two signals down at base-band...our "desired" signal would be interfered with by any signal at its "image" on the other-side of the oscillator's frequency!

And if we were to consider the Mixer's input to be a band of frequencies:


You can see the spectrum fold-back with the result being the desired signal and its undesired image occupying the same base-band frequencies.  A single-sided spectrum graph has no negative frequencies, and any "calculated" negative frequencies become positive frequencies via the Trig identity: cos(−ωit) = cos(ωit).

We can get around this image problem by working in the domain of Complex Numbers (numbers with a real and an imaginary component).  Specifically, we will use exponentials with complex arguments.


Complex Exponentials -- A Quick Review of Some Important Identities:

Euler's Formula:

e = cos(θ) + jsin(θ)

Similarly,

e−jθ = cos(θ) - jsin(θ)

From Euler's Formula it can be shown that:

cos(θ) = (e + e−jθ)/2

sin(θ) = j(e−jθ − e)/2

Let's consider a real signal at a single frequency fo (Hz), and let's express this signal simply as a cosine: cos(2πfot).

Using the identities above this signal can be expressed in exponential form:

cos(2πfot) = (ej2πfot + e−j2πfot)/2

Below is a representation, in the complex frequency-domain, of this signal :

And, for completeness, here are a two more illustrations:

First, to complement the cosine representation above, here is a complex frequency-domain representation of a sine wave signal of the same frequency:

Second, we can use both of these illustrations of the signals in the complex frequency-domain to generate a visual representation of Euler's Formula, showing how the imaginary sine terms are rotated (when multiplied by j) to the real axis and then added to the real cosine terms:

(Click on image to enlarge)

Note that multiplying sin(2πfot) by j rotates the sine's complex frequency-domain imaginary components "clockwise" by 90 degrees to the real plane. If we were to instead multiply sin(2πfot) by -j, the rotation would be 90 degrees counter-clockwise, with the results again being on the real plane, but pointing in the opposite direction, and our final result (after adding the real components together) would represent Euler's Formula for a negative frequency, -fo, instead of fo.


Frequency Conversion using Complex Numbers in Exponential Form:

Let's use the above equations to shift signal frequencies.

First, for ease of demonstration, let's define an input RF signal, x(t), to be a simple cosine at a single frequency, fi Hz.  I.e.:

 x(t) = cos(2πfit)

To minimize my typing, I will express this signal's frequency as its radian equivalent, where ωi = 2πfi.

x(t) = cos(ωit)

Using the identities above we can express cos(ωit) as the sum of two complex exponential numbers:

cos(ωit) = (eit + e−jωit)/2

Now let's now define our oscillator's signal as a complex exponential:

eot

(Note that from Euler's Formula eot  = cos(ωot) + jsin(ωot)).

Our next step is to multiply together the input signal and the oscillator signal.  We will call the output y(t).

y(t) =  cos(ωit) * eot

Replacing the input signal with its equivalent complex exponential form, the output equation becomes:

y(t) = [(eit + e−jωit)/2]*eot

Finally, let's finish the multiplying.  The result is:

y(t) = (ej(ωio)t + ej(−ωio)t)/2

Note that the frequency components in the arguments of both exponentials have been shift up by ωo.

By the way, we can use Euler's Formula to express this result in terms of sines and cosines:

y(t) = [cos((ωio)t) + jsin((ωio)t)]/2 + [cos((-ωio)t) + jsin((-ωio)t)]/2

You can also derive the same result using only sines, cosines, and trigonometric identities and not complex exponentials, but the math is more cumbersome.


OK, so an NCO's output that is a complex-exponential with an argument whose frequency is +ωwill shift the incoming signal's frequency up by ωo.  What happens if the NCO's frequency is negative, i.e. -ωo?

Using the same approach as above, the DDC's output can be shown to be:

y(t) = (ej(ωi−ωo)t + ej(−ωi−ωo)t)/2

In other words, both of the input signal's complex exponentials are shifted down in frequency by ωo. Voila, a Digital Mixer!

Again, note that y(t) can be expressed as the sum of sines and cosines.  Using the identities at the start of this post:

y(t) = [cos((ωio)t) + jsin((ωio)t)]/2 + [cos((ωio)t) - jsin((ωio)t)]/2

which is exactly equivalent to y(t) = (ej(ωi−ωo)t + ej(−ωi−ωo)t)/2.


Mixing with Complex Exponentials:

With a view towards understanding SDR building blocks, let's look at a Digital Mixer using the down-conversion math I've just discussed, and which shifts signal frequencies in the digital (rather than analog) realm.

Below is a Digital Mixer block diagram using complex numbers.  Let's drive the RF input with a simple cosine signal, cos(ωot):


Note that the oscillator's output is a complex exponential with a negative frequency in its argument.  This negative frequency, as I've discussed earlier in this post, will down-convert incoming RF.

The input signals' spectrum (shown below as two-sided, with negative frequencies, per the frequencies in the complex arguments in the exponential form of the input signal) will shift down:

(Click on image to enlarge)

The illustration below shows a more general case for a band of frequencies at the DDC's input:

(Click on image to enlarge)

Note that, unlike the analog mixer described at the start of this post, this spectrum has both positive and negative frequencies.  In other words, we do not (yet) have an issue with "image wrapping" while we remain in the complex domain.

Another take on the same topic, from "Complex Signal Processing is Not -- Complex," by Ken Martin, showing the same:


Note (again) that the input consists of only real, not complex, numbers, but the output Y(t) will be in complex form, with both real and imaginary components.

Regarding the mixer (c) in the image above, we can express its two outputs (yr(t) and yq(t)) in terms of sines and cosines.

First, for simplicity of analysis let's define the input xr(t) to be a simple cosine at frequency ωr:

x(t) = cos(ωrt)

Noting that the oscillator frequency is ωi in this example, the output yr(t) is therefore:


yr(t) = cos(ωrt)*cos(ωit)

which, using trig identities, expands to:

yr(t) = cos((ωr−ωi)t)/2 + cos((ωri)t)/2

Now let's do the same to derive yq(t), the imaginary term...noting that −sin(ωit) = sin(−ωit), yq(t) becomes:

yq(t) = sin((ωr−ωi)t)/2 − sin((ωri)t)/2

Is this result equivalent to the result derived (above) using complex-exponential equations?

Essentially, yes it is!

Let's multiply the yq(t) channel by j (i.e. add a phase shift of 90 degrees with, say, a Hilbert Transform) and call this output yq(t)' (note the 'prime').  Its equation is:

yq(t)' = jsin((ωr−ωi)t)/2 − jsin((ωri)t)/2

If we then add yr(t) and yq(t)', the result is:

yr(t) + yq(t)' = [cos((ωr−ωi)t) + jsin((ωr−ωi)t)]/2 + [cos((ωri)t)  jsin((ωri)t)]/2

Which, from Euler's Formula, we know is exactly equivalent to:

yr(t) + yq(t)' = (ej(ωr−ωi)t + ej(−ωr−ωi)t)/2.

and which is exactly equivalent in form to the equation we derived earlier:

y(t) = (ej(ωi−ωo)t + ej(−ωi−ωo)t)/2

In other words, the trigonometric signals representing yr(t) and yq(t) are the fundamental mathematical elements (when the sine terms are multiplied by j) that constitute the Digital Mixer's operation when expressed in complex-exponential form.


Links and Other Resources:


Representing a signal as the sum of two exponentials:  http://ece.mst.edu/media/academic/ece/documents/classexp/ee216labs/EE216_Lab4.pdf

The Significance of Negative Frequencies in Spectrum Analysis, Robert Marcus, IEEE Transactions on Electromagnetic Compatibility, Dec. 1967.  (A copy can be found here).

Good tutorial on Complex Number in Radio applications:  Complex Signal Processing is Not -- Complex, Ken Martin


Standard Caveat:

I could have easily made a mistake in any of the above text, equations, or drawings.  If something looks wrong or is confusing, please feel free to contact me.  Thanks!

Tuesday, October 11, 2016

More Notes on Directional Couplers for HF -- The Twin-Lead "Twin-Lamp" SWR Indicator

The Twin-Lead "Twin-Lamp," by W4HVV

At a recent swapmeet someone asked me how the venerable dual light-bulb "twin-lead" SWR indicator worked.  Although I was familiar with the device, I hadn't looked into its theory of operation, and so I said that it was probably similar to the Monimatch (described here) because, even though it used a length of twin-lead as its sensing element, that length was very short compared to an HF wavelength and thus it could be analyzed from a "lumped-element" perspective using capacitive and inductive coupling, rather than as a transmission line.

But the question made me curious as to what the analysis would be, and I decided to delve deeper...

The 'Twin-Lead "Twin-Lamp"' SWR indicator was a very simple device designed for use with twin-lead (or open-wire) transmission lines, and it used two inexpensive flashlight bulbs as Forward and Reflected Power indicators.  To my knowledge, it was first mentioned in an article by Charles Wright, W4HVV, in the October, 1947 issue of QST (The "Twin-Lamp" -- you can find a copy of the article here).  It then appeared in later editions of the ARRL's "The Radio Amateur's Handbook (up through 1961), as well as in editions of the "Radio Handbook" published by Editors and Engineers (such as the 13th edition, published in 1951, which I have).

The W4HVV's "Twin-Lamp" SWR Indicator is pictured above.  Below is a sketch of a similar design, for the 13th Edition of the Radio Handbook, published by Editors and Engineers:


In other words, the SWR indicator consists of a short length of twin-lead with two lamps attached to it.  The lamps can be attached at either end, or in the center.


Per W4HVV, the configuration shown above as (A) has greater sensitivity than configuration (B), no doubt due to the direct (rather than capacitive) connection of the top of the detection-loop to the transmission line.

W4HVV does an excellent job explaining the detector's operation, and I've included it below (from the original QST article, via the RF Cafe website).  First, the figures he references:

(Click on image to enlarge)
Figure 1

And here is his explanation (I've added some formatting changes for clarity):

Referring to Fig. 1-A, a current, IL, in the line would induce a current, I1, in a loop near the line, as shown. If the reactance of the loop is small compared to the resistance of the bulbs A and B, the current I1 will lag IL by 90°. This current will, of course, be the same through lamps A and B, and will cause them to burn with equal brightness if they are identical.

Now from Fig. 1-B, we see that bulbs A and B are across the line and in series with a small capacity C. This capacity is, of course, the distributed capacity between the loop and the line. If the reactance of this capacity is large compared to that of A and B the current I2 will flow and will lead the voltage across the line by 90°. If A and B are identical the current will divide equally between them.

Since I1 lags IL. by 90° and I2 leads EL by 90°, it is apparent that if IL and EL are in phase with each other, I1 and I2 will be exactly out of phase.

Fig. 1-C is a combination of the circuits explained above. Condenser C is the capacity between the wires of the loop and the line. Currents I1 and I2 are shown as they appear in Figs. 1-A and 1-B. It is now evident that bulb A will light from the sum of I1 and I2 and bulb B will light from the difference between these two currents. This is the case for a wave traveling toward the right. In the case of a wave traveling toward the left, the currents will add in bulb B and tend to cancel in bulb A. Thus the device is a form of "directional coupler." When the line is terminated on the right-hand side (marked "load" in Fig. 1-C) by a resistance equal to the characteristic impedance of the line, there is no reflected wave and only bulb A will light. If the load is something different, there will be some reflected energy, and lamp B will burn along with A, the relative brilliance depending upon the relative magnitudes of the transmitted and reflected energy. These facts are what make the device so useful as a standing-wave indicator.

In the foregoing discussion, three conditions were set up: 
  1. bulbs A and B should be identical; 
  2. the reactance of the loop should be small compared to the impedance of A and B; and 
  3. the reactance of the coupling capacity should be high compared to the bulb impedance. 
To satisfy the first, bulbs of the same characteristics were used, and in the interests of sensitivity, these were 2-volt 60-ma. flashlight bulbs. For the second and third considerations, the length of the coupling loop must be kept short compared to a wavelength. It was found that, for 50-Mc. operation and a transferred power of about 20 watts, a loop length of about 4 inches was a good compromise between sensitivity and the satisfaction of the above conditions. For 28 Mc. it can run a few inches longer, and at 144 Mc. an inch or so shorter. In any event, the length is not critical.

A Closer Look...

Let's dive a bit deeper and see if we can't derive some equations to describe the operation of the "Twin-Lamp".

I'm going to use the principle of Superposition (a fundamental principle in Linear Network Theory and an essential tool for circuit analysis).  I'll first look at how the voltage across the transmission line creates currents in the two lamps of the detector (independent of the current through the transmission line).  I'll then look at how the current through the transmission line (independent of the voltage across the line) creates its own currents in the two lamps.  And then I'll combine these two currents, calculated independently, to get the final aggregate lamp currents.

First, let's consider a twin-lead (or open-wire) transmission line driven by a source at one end and terminated by a load (Zload) at the other end:


If Zload differs from the characteristic impedance of the transmission line (Zo), then there are reflections along the transmission line and, if we were to measure current and voltage at an arbitrary point along the transmission line, we would see an impedance, Zload' (i.e. Zload prime), where the value of Zload' changes as we move along the transmission line, and which only equals Zload at distances equal to integer half-wavelengths as we move away from the load back towards the generator.

(Click on images to enlarge)

So, if we were to measure V and I at the (arbitrary) point shown above, it would appear to us that we had a load of impedance Zload' attached at that point, so that the transmission-line circuit can be modeled now as a much shorter line with a new load, Zload':


where:  Zload' = V/I, measured at that point.

What happens if we put our "Twin-Lamp" SWR indicator at that point, so that it measures the same V and I that creates Zload?  (Remember, the length of the Twin-Lamp detector should be significantly shorter than the wavelength of the signal being measured to ensure that the I and V it measures are essentially the same as those at Zload' ).

(Click on image to enlarge)

First, let's look at the currents through the lamps due to the voltage across the transmission line (Ilamp-C).  We can consider the bulbs to be capacitively coupled to the transmission line and, if the bulbs have identical impedances, then the currents through them will be equal and in the same direction:

(Click on image to enlarge)

The circuit is a simple voltage divider, and thus the current Ic is equal to the voltage across the line at that point divided by the sum of the series-impedances across that point:

Ic = V/(1/jωC + (Rlamp || Rlamp)+ 1/jωC)

Ic = V/(Rlamp/2 + 2/jωC)

if (2/jωC) >> (Rlamp/2) -- per W4HVV's third condition, above (that is, if the capacitive reactance is much greater than the lamp resistance), then the equation reduces to:

Ic = V*jωC/2

Assuming the impedances of the two lamps are identical, then Ic splits equally through each lamp branch:

Ilamp-C = Ic/2 = V*jωC/4

Now let's look at our second lamp-current factor: lamp current due to transmission-line current (Ilamp-L).  The transmission-line current inductively couples to the detector loop:

(Click on image to enlarge)

If the reactance of the mutual coupling is very small compared to the bulb resistances (per W4HVV's second condition, above), then this coupling can be modeled as two voltage sources (refer to this post as to why):

(Click on image to enlarge)

The lamp current due to inductive coupling, Ilamp-L is simply the current in the detector's loop, and it can be derived as follows:

Ilamp-L = Vinduced/(Rlamp +  Rlamp)

therefore,

Ilamp-L = 2*jωM*I/(2*Rlamp)

substituting V/Zload' for I and reducing,

Ilamp-L = jωM*V/(Rlamp*Zload')


So, we've calculated the currents due to capacitive coupling and due to inductive coupling.  Now let's combine them and calculate the voltage across each lamp:

(Click on image to enlarge)

Notice that the two current-components through lamp-F are in the same direction.  Therefore they add, and the voltage across this lamp can be calculated as:

Vlamp-F = (Ilamp-C + Ilamp-L)*Rlamp  

But the current-components through lamp-R are in opposite directions and therefore subtract.  The voltage across this lamp can be calculated as:

Vlamp-R = (Ilamp-C - Ilamp-L)*Rlamp     

If the transmission-line is properly terminated in a load equal to the line's characteristic impedance Zo, then the SWR should be 1:1 and lamp-R should be extinguished -- the voltage across it should be zero.  Therefore, substituting Zo for Zload' and setting Vlamp-R to 0 volts, our last equation becomes:

0 = (Ilamp-C - Ilamp-L)*Rlamp 
    
0 = (V*jωC/4 - jωM*V/(Rlamp*Zo))*Rlamp 

Which reduces to:

0 = C/4 - M/(Rlamp*Zo

This last equation gives us the relationship we need to design the appropriate values of capacitive and inductive coupling between the "Twin-Lamp" detector and the transmission line:

4*M/C = Rlamp*Z

Note the similarity between this equation and the equation derived for the monimatch:

M/C = R1*Zo 


Other notes:

The analysis above (and W4HVV's conditions) assume that the resistance of the two bulbs is identical.  But a bulb's resistance should increase as its filament heats up, so there will be a difference in the resistances of an illuminated "Forward" lamp compared to a dark "Reflected" lamp.  This difference shouldn't affect the capacitive coupling currents (as long as the capacitive reactance is significantly greater than the "hot-filament" resistance), but it will affect the current due to inductive coupling.  In this case (of unequal lamp resistances), Ilamp-L becomes:

Ilamp-L = 2*jωM*V/((Rlamp-F + Rlamp-R)*Zload')

and thus the final equation changes to:

8*M/C = (Rlamp-F + Rlamp-R )*Z

How will this difference affect the actual SWR reading?  I don't know.

As for the other conditions mentioned by W4HVV, if this device's length is kept short, then the overall capacitive coupling should be fairly small, and W4HVV's third condition of capacitive reactance being significantly larger than lamp resistance should be met.

As for W4HVV's second condition, that loop-reactance should be kept small compared to the reactance of the bulbs, I'm not sure how well this condition is met in this design, but as long as the "Reflected" bulb is dark when the line is terminated with a resistance equal to the line's characteristic impedance, Zo, I wouldn't worry too much -- after all, this device is not meant to be a laboratory-grade instrument!

And when verifying the operation of this type of SWR Indicator by terminating the transmission line with a resistive (non-inductive) load whose value equals the transmission line's characteristic impedance, Zo, (to ensure that the "Reflected" bulb is dark under "match" conditions), note that the actual Zo of twin-lead or ladder-line might differ from its assumed value.  For example, 450-ohm ladder-line might be closer to 400 ohms.

But, as W4HVV points out, his "Reflected" bulb typically did not begin to light up until SWR was at least 1.5:1, which represents a significantly larger difference in impedances than 400 ohms compared to 450 ohms.

OK, that's it for this analysis!


Some Twin-Lead SWR Indicator articles:

The "Twin-Lamp," Wright, W4HVV, QST, Oct., 1947

"The Eyes Have It," Paddon, VE3QV, QST, Oct., 1948

"The Coax Twin-Lamp," Keay, W0SJK, QST, Nov., 1948

"An Improved Twin-Lamp", Fisher, VE3ALQ, QST, Oct., 1949

"Measuring Center Impedance of Antennas with the "Twin-Lamp," Gross, W2OXR, QST, May, 1950

"The Balanced Twin-Lamp," Wood, K2BUZ, QST, Nov., 1956

"A Reflectometer for Twin-Lead," Brown, W6HPH, QST, Oct., 1980


Links to my Directional Coupler blog posts:

Notes on the Bruene Coupler, Part 2

Notes on the Bruene Coupler, Part 1

Notes on HF Directional Couplers

Building an HF Directional Coupler

Notes on the Bird Wattmeter

Notes on the Monimatch 


And some related links from my Auto-Tuner posts:

Part 5:  Directional Coupler Design

Part 6:  Notes on Match Detection

Part 8:  The Build, Phase 2 (Integration of Match Detection)


And other links:

Modeling RF transformers


Final Caveats:

As always, I might have made a mistake in my equations, assumptions, or interpretations.  If you see anything you believe to be in error, or if anything is confusing, please feel free to contact me.