Thursday, July 13, 2017

An FPGA SDR HF Transceiver, Part 7 -- Schematics, RX Signal Chain

In this seventh blog post in my FPGA SDR Transceiver series, I will describe the Receiver input circuitry -- the Receiver's Signal Chain, prior to the ADC:

  • RX Attenuator
  • Broadcast-Band Filter.
  • Anti-Aliasing Filter
  • Preamp and ADC Driver

(Part 6 of this series is here: Part 6)

But before I begin, let me again acknowledge Dick Benson, W1QG.  Dick is the father of this design, and although I've made some modifications to the FPGA logic, the underlying architecture and the vast majority of the Simulink implementation is Dick's.

This post is not yet finished and should be considered to be a

A note regarding the schematics...

These schematics were drawn using the Lite version of Cadence's Orcad Capture.  This is the free version of the program, and it limits a schematic's number of nets to 75 and the number of parts to 60 (limitations which apply if you want to save the design, which I always do).

Because this radio design has many more nets and parts than the 75/60 limit specified by Cadence, I have broken the overall design into smaller "bite size" schematics, each  independent of the others and each drawn on a single A-size sheet.

But because I've broken up the design into smaller independent pieces, I can not use Capture's Design Rule Checker to check the overall design for design flaws.  Therefore, there is the possibility that errors have crept into the schematics.  So be aware!

Block Diagram:

(Click on image to enlarge)

RX Attenuator:

(Click on image to enlarge)

Broadcast-Band Filter:

Anti-Aliasing Filter:

Preamp and ADC Driver:

The receiver's front-end gain-stage consists of a Preamp and ADC driver providing roughly 34 dB of gain to the ADC input (max ADC input is +7 dBm for ADC full-scale).

The Preamp consists of two Mini-Circuit's GALI-74 preamps connected in a push-pull configuration (to minimize second-order distortion, compared to a single-ended preamp).  Its gain is about +24 dB:

(Click on image to enlarge)

This stage was actually scavenged from a scrapped TCI board.  Using tin-snips, I cut out the push-pull GALI-74 section of the board from the TCI PCB, removed the unnecessary parts, and added SMA connectors and a two-pin header for power:

Dick's second gain stage, the ADC Driver, is shown below.  It provides an additional 10 dB of gain:

(Click on image to enlarge)

Each transistor is biased at about 50 mA of collector current.

Here's my implementation of this circuit:

To keep the radio's design simple, there is minimal front-end filtering (just an anti-aliasing filter and a broadcast-band reject filter).  So it is very important that the receiver's front end have good IM2 and IM3 performance (the reason why is explained in a bit more detail later in this post, when Dick describes his LTC6433 testing).

Here are my measurements (using my 8568B) of IM3 and IM2 performance of the GALI-74 preamp cascaded with the push-pull ADC driver.  Note that the levels are set so that the PEP output of the cascaded stages is about +7 dBm, which is the level required to drive the ADC input to full-scale:



*** add 9V regulator schematic

For comparison, here are Dick's measurements (measured with his own 8568B) of the IM3 and IM2 performance3 of his GALI-74 preamp cascaded with the push-pull ADC Driver:

Per Dick:  IMD2 is now about 84dB down from PEP and I am pleased with that result.    

For completeness, Dick also ran a Noise Figure measurement on his GALI-74 preamp cascaded with the push-pull ADC Driver:

Other Design Notes:  LTC6433 Testing:

Before Dick settled on the Push-Pull GALI-74 preamp, he tested some other ADC front-end designs.  One was the LTC6433.  Here are his notes on that device...

I took the opportunity to make a few measurements on an LTC 6433 demo board (DC2168a).

 It definitely has impressive odd order IMD performance:

But, even-order is equally important in this application --  the radio's "front end" is essentially "wide open" in that signals from 3 to 30 MHz get into the amplifier chain before the ADC.

Icom put banks of bandpass filters in line:
       15 discrete band-pass filters
          The RF Direct Sampling is protected by an array of bandpass filters.
           The signal passes through one of the fifteen bandpass filters, where signals outside the passband are rejected.

Well, that is not for me !!! 

Consequently, the even order IMD is important because strong out of band signals can mix (sum) to generate interference.

For this test, the generators output levels remained the same so that a 7 dBm PEP signal (full scale on ADC) was coming out of the LTC 6433. BUT, the signal frequencies were changed to 9 and 19 MHz so that the sum term would land at 28 MHz: 

As can be seen, the IMD2 term is loud and clear being 53+7 = 60 dB down from the PEP output.

Not bad, but not good, and no where near as nice as the IMD3 performance.

The main problem is the ADC Demo board  is a single ended 50 ohm input.  My solution to this was to build a push-pull class AB driver.

The driver, however, does not have enough gain (it is 10 dB) so it must be preceded with about 24 dB more gain.

Vlad Dvorkin's (KB9OLM)  recommendation of the GALI 74+  worked well BUT it also was single ended and had IMD2 performance that was not on par with its IMD3.  The solution: push-pull GALI 74s !  

The IMD2 and IMD3 of the overall front end are now comfortably better than 80 dB which is good enough for me! 

Other Design Notes:  Intrinsic Distortion, HP 8568B:

Before making IM3 and IM2 measurements, it is always useful to first check the distortion of the measurement system itself.  Here is an example of the intrinsic distortion of Dick's HP 8568B Spectrum Analyzer, with signal levels set to be equivalent to the FPGA SDR's ADC full-scale input level.

Note that some amount of attenuation (set via the 8568B's attenuator) is required to minimize the Spectrum Analyzer's distortion.

Here are Dick's notes:

As a check of the measurement instrumentation I ran IM3 and IM2 measurements on the 8586B. 

The synthesizers generating the two RF signals were each set to +4dBm out. There is 3dB loss in the combiner so this gives the desired 7 dBm PEP.



This can be improved:  IM2 drops essentially into the noise  with the 8568b attenuator set to 40 dB.  And some averaging is helpful:

In THEORY, it should drop 20dB, but theory has its limits.

The bottom line: The measurement capability is not a limiting factor. 

Background Notes:

SDR Notes:  Weaver Modulation and Demodulation
SDR Notes:  The Mixer Mathematics of Digital Down Conversion

Posts in this Series:

Part 1: Overview
Part 2: FPGA Modulation and Demodulation
Part 3: Interpolation and Decimation Filters
Part 5: Control Interface, Etc.

Standard Caveat:

I or Dick might have made a mistake in our designs, equations, schematics, models, etc.  If anything looks confusing or wrong to you, please feel free to comment below or send me an email.

Also, I will note:

This design and any associated information is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

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